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EM MICROELECTRONIC-MARIN SA
A6130
High Efficiency Linear Power Supply with Accurate Power Surveillance and Software Monitoring
Features

Highly accurate 5 V, 100 mA guaranteed output Low dropout voltage, typically 380 mV at 100 mA Low quiescent current, typically 155 A Standby mode, maximum current 340 A (with 100 A load on OUTPUT) Unregulated DC input can withstand -20 V reverse battery and +60 V power transients Fully operational for unregulated DC input voltage up to 26 V and regulated output voltage down to 3.0 V Reset output guaranteed for regulated output voltage down to 1.2 V No reverse output current Very low temperature coefficient for the regulated output Current limiting Comparator for voltage monitoring, voltage reference 1.17V 2.2% voltage reference accuracy at +25C 4.2% voltage reference accuracy from -40 to +85C Programmable reset voltage monitoring Programmable power on reset (POR) delay Watchdog with programmable time windows guarantees a minimum time and a maximum time between software clearing of the watchdog Time base accuracy 10% System enable output offers added security TTL/CMOS compatible -40 to +85C temperature range DIP8 and SO8 packages
lated output voltage as low as 1.2 V. The watchdog function monitors software cycle time and execution. If software clears the watchdog too quickly (incorrect cycle time) or too slowly (incorrect execution) it will cause the system to be reset. The system enable output prevents critical control functions being activated until software has successfully cleared the watchdog three times. Such a security could be used to prevent motor controls being energized on repeated resets of a faulty system.
Applications

Industrial electronics Cellular telephones Security systems Battery powered products High efficiency linear power supplies Automotive electronics
Typical Operating Configuration
Description
The A6130 offers a high level of integration by combining voltage regulation, voltage monitoring and software monitoring in an 8 lead package. The voltage regulator has a low dropout voltage (typ. 380 mV at 100 mA) and a low quiescent current (155 A). The quiescent current increases only slightly in dropout prolonging battery life. Built-in protection includes a positive transient absorber for up to 60 V (load dump) and the ability to survive an unregulated input voltage of -20 V (reverse battery). The input may be connected to ground or a reverse voltage without reverse current flow from the output to the input. A comparator monitors the voltage applied at the VIN input comparing it with an internal 1.17 V reference. The power-on reset function is initialized after VIN reaches 1.17 V and takes the reset output inactive after TPOR depending of external resistance. The reset output goes active low when the VIN voltage is less than 1.17 V. The RES and EN outputs are guaranteed to be in a correct state for a regu-
Fig. 1
Pin Assignment
Fig. 2
1
A6130
Absolute Maximum Ratings
Parameter
Continuous voltage at INPUT to VSS Transients on INPUT for t< 100 ms and duty cycle 1% Reverse supply voltage on INPUT Max. voltage at any signal pin Min. voltage at any signal pin Storage temperature Electrostatic discharge max. To MIL-STD-883C method 3015 Max. soldering conditions
Operating Conditions
Parameter
Operating junction temperature1) INPUT voltage 2) OUTPUT voltage 2) 3) RES & EN guaranteed 4) OUTPUT current 5) Comparator input voltage RC-oscillator programming Thermal resistance from junction to ambient 6) - DIP8 - SO8
1)
Symbol Conditions
VINPUT VTRANS VREV VMAX VMIN TSTO VSmax TSmax -0.3 to +30 V up to +60 V -20 V OUTPUT+0.3V VSS -0.3V -65 to +150C 1000V 250C x 10 s
Symbol Min. Max. Units
TJ VINPUT VOUTPUT VOUTPUT IOUTPUT VIN R -40 2.3 1.2 1.2 0 10 +85 26 C V V V mA V kW
100 VOUTPUT 1000
Table 1 Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction.
Rth(j-a) Rth(j-a)
105 160
C/W C/W
Table 2
The maximum operating temperature is confirmed by sampling at initial device qualification. In production, all devices are tested at +85C. 2) Full operation guaranteed. To achieve the load regulation specified in Table 3 a 22 F capacitor or greater is required on the INPUT, see Fig. 8. The 22 F must have an effective resistance 5 W and a resonant frequency above 500 kHz. 3) A 10 F load capacitor and a 100 nF decoupling capacitor are required on the regulator OUTPUT for stability. The 10 F must have an effective series resistance of 5 W and a resonant frequency above 500 kHz. 4) RES must be pulled up externally to VOUTPUT even if it is unused. (Note: RES and EN are used as inputs by EM test.) 5) The OUTPUT current will not apply for all possible combinations of input voltage and output current. Combinations that would require the A6130 to work above the maximum junction temperature (+85C) must be avoided. 6) The thermal resistance specified assumes the package is soldered to a PCB.
Handling Procedures
This device has built-in protection against high static voltages or electric fields; however, anti-static precautions must be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range. At any time, all inputs must be tied to a defined logic voltage level.
2
A6130
Electrical Characteristics
VINPUT = 6.0 V, CL = 10 F + 100 nF, CINPUT = 22 F, TJ = -40 to +85C, unless otherwise specified
Parameter
Supply current in standby mode Supply current 1) Supply current 1)
Symbol Test Conditions
ISS ISS ISS REXT = don't care, TCL = VOUTPUT, VIN = 0 V, IL = 100 A REXT = 100 kW, I/Ps at VOUTPUT, O/Ps 1 MW to VOUTPUT, IL = 100 A REXT = 100 kW, I/Ps at VOUTPUT, VINPUT = 8.0 V, O/Ps 1MW to VOUTPUT, IL = 100 mA IL = 100 A 100 A IL 100 mA, -40C TJ +85C 6 V VINPUT 26 V, IL = 1 mA, TJ = +85C 100 A IL 100 mA IL = 100 A IL = 100 A IL = 100 mA, -40C TJ +85C VINPUT = 4.5 V, IL = 100 A, REXT = 100 kW, O/Ps 1 MW to VOUTPUT, I/Ps at VOUTPUT TJ = +25C, IL = 50 mA, VINPUT = 26 V, T = 10 ms OUTPUT tied to VSS
Min.
Typ.
Max.
340
Unit
A A
155
400
1.7 4.88 4.85 50 0.2 0.2 40 380
Output voltage Output voltage Output voltage temperature coefficient 2) Line regulation 3) Load regulation 3) Dropout voltage4) Dropout voltage4) Dropout voltage4) Dropout supply current
VOUTPUT VOUTPUT
4.2 5.12 5.15 180 0.5 0.6 170 650
mA V V ppm/C % % mV mV mV
Vth(coeff) VLINE VL VDROPOUT VDROPOUT VDROPOUT ISS
1.2 0.05 450 200
1.6 0.25
mA %/W mA V rms
Thermal regulation 5) Current limit OUTPUT noise, 10 Hz to 100kHz
Vthr ILmax VNOISE
3.0 VOUTPUT 5.5 V, IL = 100 A. CL = 10 F + 100 nF, CINPUT = 22 F, TJ = -40 to +85C, unless otherwise specified RES and EN Output Low Voltage VOL VOL VOL VOL VOH VOH VOH VIL VIH ILI RVIN VREF VREF VREF VHY VOUTPUT = 4.5 V, IOL = 20 mA VOUTPUT = 4.5 V, IOL = 8 mA VOUTPUT = 2.0 V, IOL = 4 mA VOUTPUT = 1.2 V, IOL = 0.5 mA VOUTPUT = 4.5 V, IOH = -1 mA VOUTPUT = 2.0 V, IOH = -100 A VOUTPUT = 1.2 V, IOH = -30 A 3.5 1.8 1.0 VSS 2.0 VSS VTCL VOUTPUT TJ = +25C 20C TJ +70C 1.148 1.123 1.123 0.05 100 1.170 0.4 0.2 0.2 0.06 4.1 1.9 1.1 0.8 VOUTPUT 1 1.200 1.218 1.222 V V V V V V V V V A MW V V V mV
0.4 0.4 0.2
EN Output High Voltage
TCL and VIN TCL Input Low Level TCL Input High Level Leakage current TCL input VIN input resistance Comparator reference 6)7)
Comparator hysteresis 7)
1)
2
Table 3
If INPUT is connected to VSS, no reverse current will flow from the OUTPUT to the INPUT, however the supply current specified will be sank by the OUTPUT to supply the A6130. 2) The OUTPUT voltage temperature coefficient is defined as the worst case voltage change divided by the total temperature range. 3) Regulation is measured at constant junction temperature using pulse testing with a low duty cycle. Changes in OUTPUT voltage due to heating effects are covered in the specification for thermal regulation. 4) The dropout voltage is defined as the INPUT to OUTPUT differential, measured with the input voltage equal to 5.0 V. 5) Thermal regulation is defined as the change in OUTPUT voltage at a time T after a change in power dissipation is applied, excluding load or line regulation effects. 6) The comparator and the voltage regulator have separate voltage references (see Block Diagram Fig. 7). 7) The comparator reference is the power-down reset threshold. The power-on reset threshold equals the comparator reference voltage plus the comparator hysteresis (see Fig. 4).
3
A6130
Timing Characteristics
VINPUT = 6.0 V, IL = 100 A, CL = 10 F + 100 nF, CINPUT = 22 F, TJ = -40 to +85C, unless otherwise specified
Parameter
Propagation delays: TCL to Output Pins VIN sensitivity Logic Transition Times on all Output Pins Power-on Reset delay Watchdog Time Open Window Percentage Closed Window Time Open Window Time Watchdog Reset Pulse TCL Input Pulse Width
Symbol Test Conditions
TDIDO TSEN TTR TPOR TWD OWP TCW TCW TOW TOW TWDR TWDR TTCL Load 10 kW, 50 pF REXT = 118 kW, 1% REXT = 118 kW, 1%
Min.
Typ.
250 5 30 100 100 0.2 TWD 0.8 TWD 80 0.4 TWD 40 TWD / 40 2.5
Max.
500 20 100 110 110
Units
ns s ns ms ms
1
90 90
REXT = 118 kW, 1% REXT = 118 kW, 1% REXT = 118 kW, 1%
72 36
88 44
ms ms ms ns
150
Table 4
Timing Waveforms
Watchdog Timeout Period
Fig. 3 Voltage Monitoring
Fig. 4 4
A6130
Timer Reaction
Fig. 5 Combined Voltage and Timer Reaction
Fig. 6
Block Diagram
Fig. 7 5
A6130
Pin Description
Pin
1 2
Name
EN RES
Function
Push-pull active low enable output Open drain active low reset output. RES must be pulled up to VOUTPUT even if unused Watchdog timer clear input signal GND terminal Voltage regulator input Voltage regulator output REXT input for RC oscillator tuning Voltage comparator input
tion assumes a constant load (ie. 100 s). The transient thermal resistance for a single pulse is much lower than the continuous value. For example the A6130 in DIP8 package will have an effective thermal resistance from the junction to the ambient of about 10C/W for a single 100 ms pulse.
3 4 5 6 7 8
TCL VSS INPUT OUTPUT R VIN
Table 5
Functional Description
Voltage Regulator The A6130 has a 5 V 2%, 100 mA, low dropout voltage regulator. The low supply current (typ. 155 A) makes the A6130 particularly suited to automotive systems then remain energized 24 hours a day. The input voltage range is 2.3 V to 26 V for operation and the input protection includes both reverse battery (20 V below ground) and load dump (positive transients up to 60 V). There is no reverse current flow from the OUTPUT to the INPUT when the INPUT equals VSS. This feature is important for systems which need to implement (with capacitance) a minimum power supply hold-up time in the event of power failure. To achieve good load regulation a 22 F capacitor (or greater) is needed on the INPUT (see Fig. 8). Tantalum or aluminium electrolytics are adequate for the 22 F capacitor; film types will work but are relatively expensive. Many aluminium electrolytics have electrolytes that freeze at about -30C, so tantalums are recommended for operation below -25C. The important parameters of the 22 F capacitor are an effective series re sistance of 5 W and a resonant frequency above 500 kHz. A 10 F capacitor (or greater) and a 100 nF capacitor are required on the OUTPUT to prevent oscillations due to instability. The specification of the 10 F capacitor is as per the 22 F capacitor on the INPUT (see previous paragraph). The A6130 will remain stable and in regulation with no external load and the dropout voltage is typically constant as the input voltage fall to below its minimum level (see Table 2). These features are especially important in CMOS RAM keep-alive applications. Care must be taken not to exceed the maximum junction temperature (+85C). The power dissipation within the A6130 is given by the formula: PTOTAL = (VINPUT - VOUTPUT) . IOUTPUT + (VINPUT) . ISS The maximum continuous power dissipation at a given temperature can be calculated using the formula: PMAX = (85C - TA) / Rth(j-a) where Rth(j-a) is the thermal resistance from the junction to the ambient and is specified in Table 2. Note the Rth(j-a) given in Table 2 assumes that the package is soldered to a PCB. The above formula for maximum power dissipa6
VIN Monitoring The power-on reset and the power-down reset are generated as a response to the external voltage level applied on the VIN input. The VDD voltage at which reset is asserted or released is determined by the external voltage divider between VDD and VSS, as shown on Fig. 8. A part of VDD is compared to the internal voltage reference. To determine the values of the divider, the leakage current at VIN must be taken into account, as well as the current consumption of the divider itself. Low resistor values will need more current, but high resistor values will make the reset threshold less accurate at high temperature, due to a possible leakage current at the VIN input. The sum of the two resistors should stay below 300 k. The formula is: VRESET = VREF *(1 + R1/R2). Example: choosing R1 = 100 k and R2 = 36 k will result in a VDD reset threshold of 4.42 V (typ.). At power-up the reset output (RES) is held low (see Fig. 4). After INPUT reaches 3.36 V (and so OUTPUT reaches at least 3 V) and VIN becomes greater than VREF, the RES output is held low for an additional power-on-reset (POR) delay which is equal to the watchdog time TWD (typically 100 ms with an external resistor of 118 kW connected at R pin). The POR delay prevents repeated toggling of RES even if VIN and the INPUT voltage drops out and recovers. The POR delay allows the microprocessor's crystal oscillator time to start and stabilize and ensures correct recognition of the reset signal to the microprocessor. The RES output goes active low generating the power-down reset whenever VIN falls below VREF. The sensitivity or reaction time of the internal comparator to the voltage level on VIN is typically 5 s. Timer Programming The on-chip oscillator with an external resistor REXT connected between the R pin and VSS (see Fig. 8) allows the user to adjust the power-on reset (POR) delay, watchdog time TWD and with this also the closed and open time windows as well as the watchdog reset pulse width (TWD / 40). With REXT = 118 kW typical values are: - Power-on reset delay: TPOR is 100 ms - Watchdog time: TWD is 100 ms - Closed window: TCW is 80 ms - Open window: TOW is 40 ms - Watchdog reset: TWDR is 2.5 ms Note: the current consumption increases as the frequency increases. Watchdog Timeout Period Description The watchdog timeout period is divided into two parts, a "closed" window and an "open" window (see Fig. 3) and is defined by two parameters, TWD and the Open Window Percentage (OWP). The closed window starts just after
A6130
the watchdog timer resets and is defined by TCW = TWD OWP(TWD).The open window starts after the closed time window finishes and lasts till TWD + OWP(TWD). The open window time is defined by TOW = 2 x OWP(TWD). For example if TWD = 100 ms (actual value) and OWP = 20% this means the closed window lasts during first the 80 ms (TCW = 80 ms = 100 ms - 0.2 (100 ms)) and the open window the next 40 ms (TOW = 2 x 0.2 (100 ms) = 40 ms). The watchdog can be serviced between 80 ms and 120 ms after the timer reset. However as the time base is 10% accurate, software must use the following calculation for servicing signal TCL during the open window: Related to curves (Fig. 10 to Fig. 20), especially Fig. 19 and Fig. 20, the relation between TWD and REXT could easily be defined. Let us take an example describing the variations due to production and temperature: 1. Choice, TWD = 26 ms. 2. Related to Fig. 20, the coefficient (TWD to REXT) is 1.125 where REXT is in kW and TWD in ms. 3. REXT (typ.) = 26 x 1.125 = 29.3 kW. 4. conventional watchdogs by monitoring both software cycle time and execution. Should software clear the watchdog too quickly (incorrect cycle time) or too slowly (incorrect execution) it will cause the system to be reset. If software is stuck in a loop which includes the routine to clear the watchdog then a conventional watchdog would not make a system reset even though software is malfunctioning; the A6130 would make a system reset because the watchdog would be cleared too quickly. If no TCL signal is applied before the closed and open windows expire, RES will start to generate square waves of period (TCW + TOW + TWDR). The watchdog will remain in this state until the next TCL falling edge appears during an open window, or until a fresh power-up sequence. The system enable output, EN, can be used to prevent critical control functions being activated in the event of the system going into this failure mode (see section "Enable - EN Output"). The RES output must be pulled up to VOUTPUT even if the output is not used by the system (see Fig. 8).
The ratio between TWD = 26 ms and the (TCL period) = 25.4 ms is 0.975. Then the relation over the production and the full temperature range is TCL period = 0.975 x TWD or 0.975 x REXT , as typical value. TCL period = 1.125 a) While PRODUCTION value unknown for the customer when REXT 118 kW. b) While operating TEMPERATURE range -40C TJ +85C. 5. If you fixed a TCL period = 26 ms 26 x 1.125 = 30 kW. REXT = 0.975 If during your production the TWD time can be measured at TJ = +25C and the C can adjust the TCL period, then the TCL period range will be much larger for the full operating temperature.
Combined Voltage and Timer Action The combination of voltage and timer actions is illustrated by the sequence of events shown in Fig. 6. On power-up, when the voltage at VIN reaches VREF, the power-on-reset, POR, delay is initialized and holds RES active for the time of the POR delay. A TCL pulse will have no effect until this power-on-reset delay is completed. When the risk exists that TCL temporarily floats, e.g. during TPOR, a pull-up to VDD is required on that pin. After the POR delay has elapsed, RES goes inactive and the watchdog timer starts acting. If no TCL pulse occurs, RES goes active low for a short time TWDR after each closed and open window period. A TCL pulse coming during the open window clears the watchdog timer. When the TCL pulse occurs too early (during the closed window), RES goes active and a new timeout sequence starts. A voltage drop below the VREF level for longer than typically 5 s overrides the timer and immediately forces RES active and EN inactive. Any further TCL pulse has no effect until the next power-up sequence has completed. Enable - EN Output The system enable output, EN, is inactive always when RES is active and remains inactive after a RES pulse until the watchdog is serviced correctly 3 consecutive times (ie. the TCL pulse must come in the open window). After three consecutive services of the watchdog with TCL during the open window, the EN goes active low. A malfunctioning system would be repeatedly reset by the watchdog. In a conventional system critical motor controls could be energized each time reset goes inactive (time allowed for the system to restart) and in this way the electrical motors driven by the system could function out of control. The A6130 prevents the above failure mode by using the EN output to disable the motor controls until software has successfully cleared the watchdog three times (ie. the system has correctly restarted after a reset condition).
Timer Clearing and RES Action The watchdog circuit monitors the activity of the processor. If the user's software does not send a pulse to the TCL input within the programmed open window timeout period a short watchdog RES pulse is generated which is equal to TWD / 40 = 2.5 ms typically (see Fig. 5). With the open window constraint new security is added to
7
A6130
Typical Application
Fig. 8
OUTPUT Current versus INPUT Voltage
Fig. 9
8
A6130
TWD versus Temperature at 5 V TWD versus R at 5 V
Fig. 10 TWD versus VOUTPUT at TJ = +25C TWD versus R at TJ = +25C
Fig. 11
Fig. 12
Fig. 13
9
A6130
10
A6130
TWD versus VDD at TJ = +85C TWD versus R at TJ = +85C
Fig. 15 TWD versus VOUTPUT at TJ = -40C TWD versus R at TJ = -40C
Fig. 16
Fig. 17
Fig. 18 11
A6130
TWD Coefficient versus REXT at TJ = +25C
Fig. 19 REXT Coefficient versus TWD at TJ = +25C
Fig. 20
12
A6130
Package and Ordering Information
Dimensions of 8-pin SOIC Package
Dimensions in mm Min. Nom. A 1.35 1.63 A1 0.10 0.15 B 0.33 0.41 C 0.19 0.20 D 4.80 4.93 E 3.80 3.94 e 1.27 H 5.80 5.99 L 0.40 0.64
Max 1.75 0.25 0.51 0.25 5.00 4.00 6.20 1.27 Fig. 21
Dimensions of 8-pin plastic DIP Package
Dimensions in mm Min. Nom. A A1 0.38 A2 2.92 3.30 b 0.35 0.45 b2 1.14 1.52 B3 0.76 0.99 C 0.20 0.25 D 9.01 9.27 E 7.62 7.87 E1 6.09 6.35 e 2.54 eA 7.62 eB L 2.92 3.30
Max 5.33 4.95 0.56 1.78 1.14 0.35 10.16 8.25 7.11
10.92 3.81 Fig. 22 13
A6130
Ordering Information When ordering please specify complete part number. Part Number Package Delivery Form Package Marking (first line) A6130DL8A 8-pin plastic DIP Stick A6130 A6130SO8A 8-pin SOIC Stick 6130A A6130SO8B 8-pin SOIC Tape & Reel 6130A
EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date version.
E. & O.E. Printed in Switzerland, Th (c) 2002 EM Microelectronic-Marin SA, 03/02, Rev. G/343
EM 14 Microelectronic-Marin SA, CH-2074 Marin, Switzerland, Tel. +41 - (0)32 75 55 111, Fax +41 - (0)32- 75 55 403

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